1. Field of the Invention
The present invention relates to a display device, and more particularly, to a gate driver for a display device.
2. Description of the Related Art
Research has been actively made on display devices, such as liquid crystal display (LCD) or organic electro-luminescence (EL) display device, which can display an image by driving pixels arranged in an active matrix form. Specifically, in the LCD, an image is displayed by providing data signals relating to image information to pixels arranged in an active matrix form and controlling an optical transmittance of a liquid crystal layer is controlled.
The LCD includes a liquid crystal panel with pixels arranged in a matrix, and a driving circuit for driving the liquid crystal panel. In the liquid crystal panel, gate lines and data lines cross one another. Crossings of the date lines with the data lines define pixel regions. A switching thin film transistor (TFT) and a pixel electrode electrically connected to the TFT are provided in each pixel region. The TFT has a gate connected to one of the gate lines, a source connected to one of the data lines, and a drain connected to the pixel electrode.
The driving circuit includes a gate driver for supplying scan signals (e.g., gate signals) to the gate lines, and a data driver for supplying video signals to the data lines. The gate driver supplies the scan signals sequentially to the gate lines to select one line of pixels to be driven during a horizontal period. The data driver supplies the video signals to the selected data line.
An image is displayed on the LCD panel by adjusting the optical transmittance of the liquid crystal layer in accordance with an electric field between the pixel electrode and the common electrode. The applied electric field depends on the video signal applied to each pixel. Thus, an image corresponding to the video signal supplied to each pixel is displayed.
LCDs have been developed with built-in gate driver and/or data driver to reduce manufacturing cost. For example, in forming the TFTs, the gate driver is formed concurrently with the fabrication processes for the TFT. In addition, the data driver may also be built concurrently with the LCD fabrication processes.
FIG. 1 shows a block diagram of a gate driver of an LCD according to the related art. Referring to FIG. 1, the gate driver includes a plurality of stages ST1 to STn for supplying scan signals Vg1 to Vn, respectively. Also, the data driver may include a plurality of stages. The stages ST1 to STn are electrically connected in cascade to an input line that provides a start pulse SP to the first stage ST1. Thus, the first stage is supplied with the start pulse SP. Each of the stages ST1 to STn is also electrically connected to three out of four 4-phase clock signals C1 to C4. Moreover, output terminals of the stages ST1 to STn are electrically connected to the gate lines GL1 to GLn for supplying the scan signals Vg1 to Vgn to the gate lines GL1 to GLn, respectively. Further, the scan signal, one of Vg1 to Vgn, from each of the stages ST1 to STn is also supplied to the next stage. For example, the scan signal Vg1 from stage ST1 is supplied to stage ST2; the scan signal Vg2 from stage ST2 is supplied to stage ST3; and so on.
FIG. 2 is a circuit diagram of the stages illustrated in FIG. 1. Referring to FIG. 2, the first stage ST1 is electrically connected to first, third and fourth clock signals C1, C3 and C4. The first stage ST1 includes a first controller 11 for controlling a non-inverting node Q in response to the start pulse SP and the fourth clock signal C4, a second controller 13 for controlling an inverting node QB in response to the third clock signal C3 and the start pulse SP, and an output unit 15 for selectively outputting one of the first clock signal C1 and a first power supply voltage VSS in response to voltages of the non-inverting node Q and the inverting node QB.
The first controller 11 includes a first transistor T1 diode-connected between the start pulse SP and a second transistor T2. The second transistor T2 provides an electrical path from the diode-connected transistor T1 to a non-inverting node Q. A third transistor T3 provides an electrical path from the non-inverting node Q to the voltage source VSS. The second transistor T2 is controlled by the fourth clock signal C4 applied to a gate of T2. Then, the second transistor T2 controls a voltage at the node Q, which is electrically connected to a gate of an output transistor T6. Thus, the second transistor T2 controls the output transistor T6 at the output unit 15. Accordingly, the first controller 11 controls the output transistor T6 of the output unit 15 through the non-inverting node Q. The output transistor T6 receives the first clock signal C1 as input. Hence, the first clock signal C1 is supplied as the first scan signal Vg1 to the gate line GL1.
The second controller 13 includes a fourth transistor T4 having as input a second power supply voltage VDD. The fourth transistor is controlled by the third clock signal C3 applied to a gate thereof. The output of the fourth transistor T4 is electrically connected to the inverting node QB. The second controller 13 also includes a fifth transistor T5, the gate of which is electrically connected to the start pulse SP. The fifth transistor T5 provides an electrical path between the inverting node QB and the power supply VSS. Thus, the second controller 13 controls the voltage at the inverting node QB through the fourth transistor T4 and a fifth transistor T5 in response to the start pulse SP and the third clock signal C3.
The second controller 13 controls a seventh transistor T7 of the output unit 15 through the inverting node QB, such that the first power supply voltage VSS is supplied as the first scan signal Vg1 to the gate line GL1. The output unit 15 includes: a sixth transistor T6 for switching the first clock signal C1 to be supplied to the gate line GL1 in response to the voltage at the non-inverting node Q; and a seventh transistor T7 for selectively supplying the first power supply voltage VSS to the gate line GL1 in response to the voltage at the inverting node QB.
Also, the first controller 11 further includes a third transistor T3 connected among the non-inverting node Q, the inverting node QB, and the input line of the first power supply voltage VSS. The third transistor T3 operates in a dual mode together with the seventh transistor T7 and controls the inverting node QB.
FIG. 3 is a voltage waveform for the stages illustrated in FIG. 1. As illustrated in FIG. 3, the 4-phase clock signals C1 to C4 are produced by sequentially delaying a phase of a clock signal by one clock period. Using three clock signals of the 4-phase clock signals C1 to C4, each of the stages ST1 to ST4 shifts the start pulse SP by one clock period and outputs the shifted start pulse as the scan signal corresponding to each of the respective stages. For example, the stages ST1 to STn are supplied with the three clock signals C1, C3 and C4 with sequentially delayed phases. Using the inputted clock signals, the stages ST1 to STn sequentially shift the start pulse SP to generate the scan signals Vg1 to Vgn.
As illustrated in FIG. 1, the stages ST1 to STn are connected in cascade to shift an input line of the start pulse, thus generating the scan signals to the gate lines GL. Specifically, the first stage ST1 is supplied with the start pulse SP, and the second to n-th stages ST2 to STn are supplied with the scan signals of their previous stages ST1 to STn−1, respectively.
The first stage ST1 receives the first, third and fourth clock signals C1, C3 and C4 whose phases are sequentially delayed by one clock period. The phase of the fourth clock signal C4 is synchronized with the start pulse SP. The start pulse SP and the first to fourth clock signals C1 to C4 have a voltage swing in a range between −5 V to 20 V. That is, the first to fourth clock signals C1 to C4 have a low voltage section of −5 V and a high voltage section of 20 V in a pulse form. Hereinafter, the low voltage section of −5 V will be referred to as a logic low voltage, and the high voltage section of 20 V will be referred to as a logic high voltage. Also, the first power supply voltage VSS has a negative voltage (−5 V), while the second power supply voltage VDD has a positive voltage (20 V). An operation of the first stage ST1 will be described below with reference to these waveforms.
During a T1 period, when the start pulse SP and the fourth clock signal C4 are simultaneously set to a high logic level, the first and second transistors T1 and T2 are turned on, so that the non-inverting node Q is charged to about 20 V. Thus, the sixth transistor T6 having the gate connected to the non-inverting node Q is gradually turned on. Also, the fifth transistor T5 is turned on by the start pulse SP of a high logic level, so that −5 V supplied through the input line of the first power supply voltage VSS is charged to the non-inverting node QB. Therefore, the third and seventh transistors T3 and T7 having gates connected to the inverting node QB are turned off. Consequently, the low voltage (−5 V) of the first clock signal C1 is supplied to the first gate line GL1 of the first stage ST1 through the turned-on sixth transistor T6, so that the gate line GL1 is charged to the logic low voltage (−5 V).
During a T2 period, the start pulse SP and the fourth clock signal C4 are set to a low logic level and the first clock signal C1 is set to a high logic level. In this case, bootstrapping phenomenon occurs due to the influence of an internal capacitor Cgs formed between the gate and source of the sixth transistor. Thus, a voltage of about 40 V is charged at the non-inverting node Q, so that the non-inverting node Q is perfectly set to the high logic level. The occurrence of the bootstrapping phenomenon is possible because the first to third transistors T1 to T3 are all turned off and thus the non-inverting node Q is in a floating state. Accordingly, the sixth transistor T6 is perfectly turned on, so that the logic high voltage (20 V) of the first clock signal C1 is rapidly charged to the first gate line GL1 connected to the first stage ST1. Thus, the first gate line GL1 is charged to the high logic level of 20 V.
During a T3 period, the first clock signal C1 is set to a low logic level and the second clock signal C2 is set to a high logic level. The voltage at the non-inverting node Q is decreased to about 20 V and the logic low voltage (−5 V) of the first clock signal C1 is charged through the turned-on sixth transistor T6 to the first gate line GL1 of the first stage ST1.
During a T4 period, the third clock signal C3 is set to a high logic level and the fourth transistor T4 is turned on. 20 V of the second power supply voltage VDD is charged at the inverting node QB, so that the third and seventh transistors T3 and T7 are turned on. Therefore, the high voltage of about 20 V charged through the turned-on third transistor T3 to the non-inverting node Q is changed into the logic low voltage of −5 V, and the logic low voltage of −5 V supplied from the input line of the first power supply voltage VSS is charged at the first gate line GL1, so that the scan signal of the low logic level appears at the first gate line GL1. This state is maintained until the start pulse SP and the fourth clock signal are again supplied in the next frame. That is, during the periods of the fourth, first and second clock signals C4, C1 and C2, the logic high voltage is outputted through the sixth transistor T6, and the non-inverting node Q maintains the logic low voltage until the start pulse SP and the fourth clock signal are supplied in the next frame from a time point when the third clock signal C3 is supplied. Also, the logic high voltage is applied to the non-inverting node QB. Consequently, the logic high voltage is maintained at the inverting node QB for most time of one frame. If the gate driver operates in this state for a long time, the seventh transistor T7 having the gate connected to the inverting node QB is degraded. Thus, the characteristics of the transistor are degraded. In a severe case, fatal damage may occur in the transistor such that the transistor does not operate. In this case, an image is poorly displayed, resulting in the degradation of the image quality.
The second stage ST2 has the same structure as that of the first stage ST1. However, the second stage ST2 operates in the same manner as the first stage ST1 by using clocks (e.g., C1, C2, C4) having different phases from the clock signals used in the first stage ST1 by one clock period and the first scan signal Vg1 of the first stage ST1. The first scan signal Vg1 supplied to the second stage ST2 is used for the same purpose as the start pulse SP supplied to the first stage ST1. Consequently, the second stage ST2 outputs the second scan signal Vg2 of the high logic level, which is shifted by one clock period compared to the first stage ST1.
The second to n-th stages ST2 to STn operate in the same manner as the above-describe first stage ST1. Therefore, the second to n-th scan signals Vg2 to Vgn are outputted to the corresponding second to n-th gate lines GL2 to GLn. The second to n-th scan signals Vg2 to Vgn are produced by sequentially shifting the logic high pulse by its width.
Therefore, during one frame, the scan signals Vg1 to Vgn are generated which have the logic high pulse shifted by the stages ST1 to STn connected to the gate lines GL1 to GLn. These procedures are repeated at each frame.
In the gate driver constructed as above, a time (20 μs) necessary to supply the scan signals Vg1 to Vgn of the high logic level to the respective gate lines during one frame period (16.67 ms) is very shortened. On the contrary, the respective gate lines GL1 to GLn supply the scan signals Vg1 to Vgn of the low logic level (−5 V) during most (90% or more) of one frame period. At this point, while the scan signals Vg1 to Vgn of the low logic level are supplied, the logic high voltage is maintained at the gate of the seventh transistor T7. That is, the logic high voltage has to be maintained at the gate of the seventh transistor T7 so as to maintain the logic low voltage at the gate line GL for most of time at every frame. Therefore, due to the repetition of the above procedures, stress voltage is accumulated at the seventh transistor, resulting in degradation.
As illustrated in FIG. 4, the stress voltage is accumulated and increased in each frame. Generally, the LCD displays an image on its screen for at least a few years or several ten years. However, the accumulated stress voltage causes degradation. Due to degradation, a threshold voltage of the seventh transistor T7 increases or decreases, reducing the mobility. Consequently, the device performance is degraded and the operation of the seventh transistor T7 is not correctly controlled. Therefore, the device displays a poor image of low quality. In addition, the LCD has shortened lifetime.